# Pastebin zmkn1VFM
From 09dcf9bbe80444bac727f905788aef4e9defc3cd Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 26 Nov 2021 09:06:15 +0100
Subject: [PATCH] Integrate/Fix ejcspii's wb_test_slave.v.

cd litex/soc/tools
./litex_sim.py
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov 26 2021 09:02:59
 BIOS CRC passed (825dea61)

 Migen git sha1: 9a0be7a
 LiteX git sha1: 85d6cb4b

--=============== SoC ==================--
CPU:		VexRiscv @ 1MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list
Available memory regions:
ROM       0x00000000 0x20000
SRAM      0x10000000 0x2000
WB_TEST_SLAVE  0x80000000 0x10
CSR       0xf0000000 0x10000

litex> mem_read 0x80000000 0x10
Memory dump:
0x80000000  20 00 00 00 de c0 ad 0b de c0 ad 0b de c0 ad 0b   ...............
---
 litex/tools/litex_sim.py        | 21 ++++++++++++++
 litex/tools/rtl/wb_test_slave.v | 49 +++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)
 create mode 100644 litex/tools/rtl/wb_test_slave.v

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 51905809..ac4663fa 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -303,6 +303,27 @@ class SimSoC(SoCCore):
         else:
             self.comb += platform.trace.eq(1)
 
+
+        class TestModule(Module):
+            def __init__(self, platform):
+                self.bus = bus = wishbone.Interface(data_width=32, adr_width=29)
+                self.specials += Instance("wb_test_slave",
+                    i_i_reset   = ResetSignal("sys"),
+                    i_i_clk     = ClockSignal("sys"),
+                    i_i_wb_cyc  = bus.cyc,
+                    i_i_wb_stb  = bus.stb,
+                    i_i_wb_we   = bus.we,
+                    i_i_wb_addr = bus.adr,
+                    i_i_wb_data = bus.dat_w,
+                    o_o_wb_data = bus.dat_r,
+                    o_o_wb_ack  = bus.ack,
+                    #o_o_wb_err = bus.err,
+                )
+                platform.add_source("rtl/wb_test_slave.v")
+
+        self.submodules.wb_test_slave = TestModule(platform)
+        self.bus.add_slave(name="wb_test_slave", slave=self.wb_test_slave.bus, region=SoCRegion(size=16, cached=False))
+
 # Build --------------------------------------------------------------------------------------------
 
 def generate_gtkw_savefile(builder, vns, trace_fst):
diff --git a/litex/tools/rtl/wb_test_slave.v b/litex/tools/rtl/wb_test_slave.v
new file mode 100644
index 00000000..3a75a0aa
--- /dev/null
+++ b/litex/tools/rtl/wb_test_slave.v
@@ -0,0 +1,49 @@
+module wb_test_slave
+(
+                input   wire                i_clk, i_reset,
+                // Wishbone inputs
+                input   wire                i_wb_cyc,
+                input   wire                i_wb_stb, i_wb_we,
+                input   wire    [31:0]  i_wb_addr,
+                input   wire    [31:0]  i_wb_data,
+                input   wire    [3:0]   i_wb_sel,
+                output  wire                o_wb_stall,
+                output  reg                     o_wb_ack,
+                output  reg         [31:0]      o_wb_data
+        //output  wire            o_wb_err
+        //
+);
+
+    reg [31:0] regs;
+  always @(posedge i_clk)
+    begin
+        if(i_reset == 1'b1)
+            regs <= 32'b0;
+        else if (i_wb_stb && i_wb_we && !o_wb_stall)
+        begin
+            regs <= i_wb_data;
+        end
+    end
+
+    always @(posedge i_clk)
+    begin
+        case(i_wb_addr)
+            32'h0: o_wb_data <= regs;
+            default: o_wb_data <= 32'h0badc0de;
+        endcase
+    end
+
+    assign o_wb_stall = 1'b0;
+
+   always @(posedge i_clk)
+    if (i_reset)
+        o_wb_ack <= 1'b0;
+    else
+        o_wb_ack <= (i_wb_stb && i_wb_cyc && !o_wb_stall);
+
+	wire _unused_ok = &{1'b0,
+                    i_wb_cyc,
+                    i_wb_sel,
+                    1'b0};
+
+endmodule
\ No newline at end of file
-- 
2.17.1