# Pastebin w5dvV9Ep The entire flow of VPR took 0.494114 seconds. icebox_hlc2asc vtr/tests/ice40/iceinv/build-ice40-top-routing-virt-HX1K/example.asc icebox_vlog -n top -p example.pcf -d vq100 vtr/tests/ice40/iceinv/build-ice40-top-routing-virt-HX1K/example_bitstream.v vtr/tests/ice40/iceinv/build-ice40-top-routing-virt-HX1K/example_bitstream.v /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.7+578 (git sha1 a7281930, x86_64-conda_cos6-linux-gnu-gcc 7.2.0 -fPIC -Os) -- Parsing `vtr/tests/ice40/iceinv/build-ice40-top-routing-virt-HX1K/example_bitstream.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend. ERROR: Found posedge/negedge event on a signal that is not 1 bit wide at vtr/tests/ice40/iceinv/build-ice40-top-routing-virt-HX1K/example_bitstream.v:53! ../../make/test-common.mk:242: recipe for target 'check' failed make: *** [check] Error 1