# Pastebin orc1lIcP
/* Generated by Yosys 0.7+596 (git sha1 83631555, clang 6.0.0 -fPIC -Os) */

(* top =  1  *)
(* src = "ffmodes.v:1" *)
module top(clk, cen, rst, ina, inb, outa, outb, outc, outd);
  (* src = "ffmodes.v:1" *)
  input cen;
  (* src = "ffmodes.v:1" *)
  input clk;
  (* src = "ffmodes.v:1" *)
  input ina;
  (* src = "ffmodes.v:1" *)
  input inb;
  (* src = "ffmodes.v:1" *)
  output outa;
  (* src = "ffmodes.v:1" *)
  output outb;
  (* src = "ffmodes.v:1" *)
  output outc;
  (* src = "ffmodes.v:1" *)
  output outd;
  (* src = "ffmodes.v:1" *)
  input rst;
  (* src = "ffmodes.v:3" *)
  wire temp0;
  (* src = "ffmodes.v:3" *)
  wire temp1;
  (* src = "ffmodes.v:33|/usr/local/bin/../share/yosys/ice40/cells_map.v:1" *)
  SB_DFFN _0_ (
    .C(clk),
    .D(temp0),
    .Q(outc)
  );
  (* src = "ffmodes.v:30|/usr/local/bin/../share/yosys/ice40/cells_map.v:2" *)
  SB_DFF _1_ (
    .C(clk),
    .D(temp1),
    .Q(outb)
  );
  (* src = "ffmodes.v:16|/usr/local/bin/../share/yosys/ice40/cells_map.v:7" *)
  SB_DFFNESS _2_ (
    .C(clk),
    .D(inb),
    .E(ina),
    .Q(temp1),
    .S(rst)
  );
  (* src = "ffmodes.v:9|/usr/local/bin/../share/yosys/ice40/cells_map.v:8" *)
  SB_DFFESR _3_ (
    .C(clk),
    .D(ina),
    .E(cen),
    .Q(temp0),
    .R(rst)
  );
  (* src = "ffmodes.v:36|/usr/local/bin/../share/yosys/ice40/cells_map.v:16" *)
  SB_DFFNS _4_ (
    .C(clk),
    .D(temp1),
    .Q(outd),
    .S(rst)
  );
  (* src = "ffmodes.v:24|/usr/local/bin/../share/yosys/ice40/cells_map.v:17" *)
  SB_DFFR _5_ (
    .C(clk),
    .D(temp0),
    .Q(outa),
    .R(rst)
  );
endmodule