# Pastebin oc6ES2Sb
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -38,6 +38,7 @@
 #define   CLK_RX_PHASE_MASK GENMASK(13, 12)
 #define   CLK_PHASE_0 0
 #define   CLK_PHASE_180 2
+#define   CLK_PHASE_270 3
 #define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
 #define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
 #define   CLK_V2_ALWAYS_ON BIT(24)
@@ -415,7 +416,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
        /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
        clk_reg = CLK_ALWAYS_ON(host);
        clk_reg |= CLK_DIV_MASK;
-       clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+       clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_270);
        clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
        clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
        writel(clk_reg, host->regs + SD_EMMC_CLOCK);