# Pastebin hUSFiOtA
NIR validation failed after nir_opt_phi_precision
4 errors:
shader: MESA_SHADER_FRAGMENT
name: GLSL1
label: android-shaders/android/gfxbench/manhattan31/384.shader_test
inputs: 1
outputs: 1
uniforms: 5
ubos: 1
shared: 0
decl_var uniform INTERP_MODE_NONE lowp sampler2D texture_unit0 (0, 0, 0)
decl_var ubo INTERP_MODE_NONE vec4[5] uniform_0 (0, 0, 0)
decl_var shader_in INTERP_MODE_NONE mediump float packed:out_texcoord0 (VARYING_SLOT_VAR0.x, 0, 0)
decl_var shader_in INTERP_MODE_NONE mediump float packed:out_texcoord0@0 (VARYING_SLOT_VAR0.y, 0, 0)
decl_var shader_in INTERP_MODE_NONE mediump vec2 packed:out_texcoord0@1 (VARYING_SLOT_VAR0.xy, 0, 0)
decl_var shader_out INTERP_MODE_NONE mediump vec4 frag_color (FRAG_RESULT_DATA0.xyzw, 0, 0)
decl_function main (0 params)

impl main {
	block block_0:
	/* preds: */
	vec1 32 ssa_45 = load_const (0x00000000 /* 0.000000 */)
	vec1 16 ssa_65 = f2fmp ssa_45
	vec1 16 ssa_62 = f2fmp ssa_45
	vec1 16 ssa_59 = f2fmp ssa_45
	vec1 16 ssa_56 = f2fmp ssa_45
	vec2 32 ssa_46 = intrinsic load_barycentric_pixel () (0) /* interp_mode=0 */
	vec2 32 ssa_47 = intrinsic load_interpolated_input (ssa_46, ssa_45) (0, 0, 160, 8388768) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=32 slots=1 mediump */	/* packed:out_texcoord0 */
	vec1 16 ssa_3 = load_const (0x000a /* 0.000001 */)
	vec1 16 ssa_4 = load_const (0x0001 /* 0.000000 */)
	/* succs: block_1 */
	loop {
		block block_1:
		/* preds: block_0 block_4 */
		vec1 32 ssa_5 = phi block_0: ssa_45, block_4: ssa_37
		vec1 16 ssa_55 = phi block_0: ssa_56, block_4: ssa_57
error: entry (../src/compiler/nir/nir_validate.c:195)

		vec1 32 ssa_6 = phi block_0: ssa_45, block_4: ssa_38
		vec1 16 ssa_58 = phi block_0: ssa_59, block_4: ssa_60
error: entry (../src/compiler/nir/nir_validate.c:195)

		vec1 32 ssa_7 = phi block_0: ssa_45, block_4: ssa_39
		vec1 16 ssa_61 = phi block_0: ssa_62, block_4: ssa_63
error: entry (../src/compiler/nir/nir_validate.c:195)

		vec1 32 ssa_8 = phi block_0: ssa_45, block_4: ssa_40
		vec1 16 ssa_64 = phi block_0: ssa_65, block_4: ssa_66
error: entry (../src/compiler/nir/nir_validate.c:195)

		vec1 32 ssa_9 = phi block_0: ssa_45, block_4: ssa_42
		vec1 16 ssa_10 = i2imp ssa_9
		vec1 1 ssa_11 = ige ssa_10, ssa_3
		/* succs: block_2 block_3 */
		if ssa_11 {
			block block_2:
			/* preds: block_1 */
			break
			/* succs: block_5 */
		} else {
			block block_3:
			/* preds: block_1 */
			/* succs: block_4 */
		}
		block block_4:
		/* preds: block_3 */
		vec1 32 ssa_12 = load_const (0x00000002 /* 0.000000 */)
		vec1 32 ssa_13 = ishl ssa_9, ssa_12
		vec1 32 ssa_14 = intrinsic load_ubo (ssa_45, ssa_13) (0, 4, 0, 0, 40) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */ /* range_base=0 */ /* range=40 */
		vec1 16 ssa_15 = f2fmp ssa_5
		vec1 16 ssa_16 = f2fmp ssa_6
		vec1 16 ssa_17 = f2fmp ssa_7
		vec1 16 ssa_18 = f2fmp ssa_8
		vec1 32 ssa_19 = load_const (0x00000028 /* 0.000000 */)
		vec1 32 ssa_20 = iadd ssa_19, ssa_13
		vec1 32 ssa_21 = intrinsic load_ubo (ssa_45, ssa_20) (0, 4, 0, 40, 40) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */ /* range_base=40 */ /* range=40 */
		vec1 16 ssa_22 = f2fmp ssa_21
		vec1 16 ssa_23 = f2fmp ssa_47.y
		vec1 16 ssa_24 = f2fmp ssa_14
		vec1 16 ssa_25 = fadd ssa_23, ssa_24
		vec1 32 ssa_26 = f2f32 ssa_25
		vec2 32 ssa_27 = vec2 ssa_47.x, ssa_26
		vec4 16 ssa_28 = (float16)tex ssa_27 (coord), 0 (texture), 0 (sampler)
		vec1 16 ssa_29 = fmul ssa_22, ssa_28.x
		vec1 16 ssa_30 = fmul ssa_22, ssa_28.y
		vec1 16 ssa_31 = fmul ssa_22, ssa_28.z
		vec1 16 ssa_32 = fmul ssa_22, ssa_28.w
		vec1 16 ssa_33 = fadd ssa_55, ssa_29
		vec1 16 ssa_34 = fadd ssa_58, ssa_30
		vec1 16 ssa_35 = fadd ssa_61, ssa_31
		vec1 16 ssa_36 = fadd ssa_64, ssa_32
		vec1 32 ssa_37 = f2f32 ssa_33
		vec1 16 ssa_57 = f2fmp ssa_37
		vec1 32 ssa_38 = f2f32 ssa_34
		vec1 16 ssa_60 = f2fmp ssa_38
		vec1 32 ssa_39 = f2f32 ssa_35
		vec1 16 ssa_63 = f2fmp ssa_39
		vec1 32 ssa_40 = f2f32 ssa_36
		vec1 16 ssa_66 = f2fmp ssa_40
		vec1 16 ssa_41 = iadd ssa_10, ssa_4
		vec1 32 ssa_42 = i2i32 ssa_41
		/* succs: block_1 */
	}
	block block_5:
	/* preds: block_2 */
	vec1 16 ssa_50 = f2fmp ssa_5
	vec1 16 ssa_51 = f2fmp ssa_6
	vec1 16 ssa_52 = f2fmp ssa_7
	vec1 16 ssa_53 = f2fmp ssa_8
	vec4 16 ssa_54 = vec4 ssa_55, ssa_58, ssa_61, ssa_64
	intrinsic store_output (ssa_54, ssa_45) (0, 15, 0, 144, 8388740) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float16 */ /* location=4 slots=1 mediump */	/* frag_color */
	/* succs: block_6 */
	block block_6:
}