# Pastebin g3L0RuPW
class UARTAppletTestCase(GlasgowAppletV2TestCase, applet=UARTApplet):
    @synthesis_test
    def test_build(self):
        self.assertBuilds()

    def write(self, iface):
        async def testbench(ctx):
            await iface.write(b"Hello")
        return testbench

    def test_loopback(self):
        assembly  = SimulationAssembly()
        iface0    = UARTInterface(logger, assembly, rx="A0", tx="A1")
        iface1    = UARTInterface(logger, assembly, rx="B0", tx="B1")

        assembly.connect_pins("A0", "B1")
        assembly.connect_pins("A1", "B0")

        assembly.add_testbench(self.write(iface0))

        async def do_it(ctx):
            print(await iface1.read(1))

        assembly.run(do_it, vcd_file="test.vcd")