# Pastebin g2KlpFSo
// Reading file 'vtr/tests/ice40/iceinv/build-ice40-top-routing-virt-HX1K/example.asc'..

module top (inout LED3, input btn);

wire n1;
// (12, 6, 'neigh_op_tnr_2')
// (12, 6, 'neigh_op_tnr_6')
// (12, 7, 'neigh_op_rgt_2')
// (12, 7, 'neigh_op_rgt_6')
// (12, 8, 'neigh_op_bnr_2')
// (12, 8, 'neigh_op_bnr_6')
// (13, 3, 'span4_vert_t_14')
// (13, 4, 'span4_vert_b_14')
// (13, 5, 'span4_vert_b_10')
// (13, 6, 'io_1/D_OUT_0')
// (13, 6, 'local_g1_6')
// (13, 6, 'span4_vert_b_6')
// (13, 7, 'io_1/D_IN_0')
// (13, 7, 'span4_vert_b_2')

wire LED3;
// (13, 6, 'io_1/PAD')

wire btn;
// (13, 7, 'io_1/PAD')

// IO Cell (13, 6, 1)
// PAD     = LED3
// D_IN_0  = 
// D_IN_1  = 
// D_OUT_0 = n1
// D_OUT_1 = 0
// OUT_ENB = 1
// CLK_EN  = 1
// IN_CLK  = 0
// OUT_CLK = 0
// LATCH   = 0
// TYPE    = 000000 (LSB:MSB)

// IO Cell (13, 7, 1)
// PAD     = btn
// D_IN_0  = n1
// D_IN_1  = 
// D_OUT_0 = 0
// D_OUT_1 = 0
// OUT_ENB = 1
// CLK_EN  = 1
// IN_CLK  = 0
// OUT_CLK = 0
// LATCH   = 0
// TYPE    = 000000 (LSB:MSB)
reg n4;
always @(posedge 0) n4 <= btn;
assign n1 = n4;


endmodule