# Pastebin f7FyPClN
module top (
	input  CLK,
	input  RX,
	output TX,
	output reg LED1,
	output reg LED2,
	output reg LED3,
	output reg LED4,
	output reg LED5,
	output LEDG_N,
	output LEDR_N
);
	parameter integer BAUD_RATE = 9600;
	parameter integer CLOCK_FREQ_HZ = 12000000;
	localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE);

	reg [7:0] buffer;
	reg buffer_valid;

	reg [$clog2(3*HALF_PERIOD):0] cycle_cnt;
	reg [3:0] bit_cnt = 0;
	reg recv = 0;

	reg LED6, LED7;
	assign LEDG_N = !LED6;
	assign LEDR_N = !LED7;

	initial begin
		LED1 = 0;
		LED2 = 0;
		LED3 = 0;
		LED4 = 0;
		LED5 = 0;
	end

	always @(posedge CLK) begin
		buffer_valid <= 0;
		if (!recv) begin
			if (!RX) begin
				cycle_cnt <= HALF_PERIOD;
				bit_cnt <= 0;
				recv <= 1;
			end
		end else begin
			if (cycle_cnt == 2*HALF_PERIOD) begin
				cycle_cnt <= 0;
				bit_cnt <= bit_cnt + 1;
				if (bit_cnt == 9) begin
					buffer_valid <= 1;
					recv <= 0;
				end else begin
					buffer <= {RX, buffer[7:1]};
				end
			end else begin
				cycle_cnt <= cycle_cnt + 1;
			end
		end
	end

	always @(posedge CLK) begin
		if (buffer_valid) begin
			case (buffer)
				"1": LED1 <= !LED1;
				"2": LED2 <= !LED2;
				"3": LED3 <= !LED3;
				"4": LED4 <= !LED4;
				"5": LED5 <= !LED5;
				"6": LED6 <= !LED6;
				"7": LED7 <= !LED7;
				"8": {LED7, LED6, LED5, LED4, LED3, LED2, LED1} <= {LED6, LED5, LED4, LED3, LED2, LED1, LED7};
				"9": {LED7, LED6, LED5, LED4, LED3, LED2, LED1} <= 7'b 1111111;
				"0": {LED7, LED6, LED5, LED4, LED3, LED2, LED1} <= 7'b 0000000;
				default: begin
					LED1 <= LED1 ^ LED2;
					LED2 <= LED2 & LED3;
					LED3 <= LED3 | LED4;
					LED4 <= ^{LED4, LED5, LED6, LED7};
					LED5 <= &{LED4, LED5, LED6, LED7};
					LED6 <= |{LED4, LED5, LED6, LED7};
					LED7 <= ~LED7;
				end
			endcase
		end
	end

	assign TX = RX;
endmodule