# Pastebin ePlMYkRJ
<------><------>assigned-clocks =
<------><------><------>/*
<------><------><------> * CPLL should run at 1200, but that is to high for
<------><------><------> * the initial dividers of most of its children.
<------><------><------> * We need set cpll child clk div first,
<------><------><------> * and then set the cpll frequency.
<------><------><------> */
<------><------><------><&cru DCLK_LCDC>, <&cru SCLK_PDM>,
<------><------><------><&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
<------><------><------><&cru SCLK_UART1>, <&cru SCLK_UART2>,
<------><------><------><&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<------><------><------><&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
<------><------><------><&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
<------><------><------><&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
<------><------><------><&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
<------><------><------><&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
<------><------><------><&cru SCLK_SDIO>, <&cru SCLK_TSP>,
<------><------><------><&cru SCLK_WIFI>, <&cru ARMCLK>,
<------><------><------><&cru PLL_GPLL>, <&cru PLL_CPLL>,
<------><------><------><&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
<------><------><------><&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<------><------><------><&cru HCLK_PERI>, <&cru PCLK_PERI>,
<------><------><------><&cru SCLK_RTC32K>;
<------><------>assigned-clock-parents =
<------><------><------><&cru HDMIPHY>, <&cru PLL_APLL>,
<------><------><------><&cru PLL_GPLL>, <&xin24m>,
<------><------><------><&xin24m>, <&xin24m>;
<------><------>assigned-clock-rates =
<------><------><------><0>, <61440000>,
<------><------><------><0>, <24000000>,
<------><------><------><24000000>, <24000000>,
<------><------><------><15000000>, <15000000>,
<------><------><------><100000000>, <250000000>,
<------><------><------><100000000>, <250000000>,
<------><------><------><50000000>, <250000000>,
<------><------><------><100000000>, <250000000>,
<------><------><------><50000000>, <50000000>,
<------><------><------><50000000>, <50000000>,
<------><------><------><24000000>, <600000000>,
<------><------><------><491520000>, <1200000000>,
<------><------><------><150000000>, <75000000>,
<------><------><------><75000000>, <150000000>,
<------><------><------><75000000>, <75000000>,
<------><------><------><32768>;
<------>};