# Pastebin ceEIFk7R
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="BLK_TL-PIO" capacity="2" xmlns:xi="http://www.w3.org/2001/XInclude">
 <!-- SB_IO inputs   -->
 <output name="D_IN" num_pins="2"/>

 <!-- SB_IO outputs -->
 <input  name="D_OUT" num_pins="2"/>

 <!-- Control signals -->
 <input  name="OUT_ENB" num_pins="1"/>

 <input  name="CEN"     num_pins="1"/>
 <clock  name="INCLK"   num_pins="1"/>
 <clock  name="OUTCLK"  num_pins="1"/>
 <input  name="LATCH"   num_pins="1"/>

 <output name="PACKAGE_PIN" num_pins="1"/>

 <!-- IO operating as an output -->
 <mode name="PAD_IS_OUTPUT">
  <pb_type name="PAD" num_pb="1">
   <input name="D_OUT" num_pins="2"/>
   <pb_type name="output" blif_model=".output" num_pb="1">
    <input name="outpad" num_pins="1"/>
   </pb_type>
   <interconnect>
    <mux>
     <port type="input" from="parent" name="D_OUT" bit="0"/>
     <port type="output" from="current" name="outpad"/>
    </mux>
   </interconnect>
   <metadata>
    <meta name="hlc_property">disable_pull_up</meta>
    <meta name="hlc_property">output_pin_type = simple_output_pin</meta>
    <meta name="hlc_property">input_pin_type = simple_input_pin</meta>
   </metadata>
  </pb_type>

  <interconnect>
   <!-- SB_IO outputs -->
   <direct>
    <port type="input" from="parent" name="D_OUT" bit="0"/>
    <port type="output" from="current" name="D_OUT" bit="0"/>
   </direct>
   <direct>
    <port type="input" from="parent" name="D_OUT" bit="1"/>
    <port type="output" from="current" name="D_OUT" bit="1"/>
   </direct>
  </interconnect>
 </mode>

 <!-- IO operating as an input -->
 <mode name="PAD_IS_INPUT">
  <pb_type name="PAD" num_pb="1">
   <output name="D_IN" num_pins="2"/>
   <output name="PIN"  num_pins="1"/>
   <pb_type name="input" blif_model=".input" num_pb="1">
    <output name="inpad" num_pins="1"/>
   </pb_type>
   <interconnect>
    <direct>
     <port type="input" from="current" name="inpad"/>
     <port type="output" from="parent" name="D_IN" bit="0"/>
    </direct>
    <direct>
     <port type="input" from="current" name="inpad"/>
     <port type="output" from="parent" name="PIN"/>
    </direct>
    <!--
    <direct>
     <source from="current" name="inpad"/>
     <sink from="parent" name="D_IN" bit="0"/>
    </direct>
     -->
   </interconnect>
   <metadata>
    <meta name="hlc_property">disable_pull_up</meta>
    <meta name="hlc_property">enable_input</meta>
    <meta name="hlc_property">input_pin_type = simple_input_pin</meta>
   </metadata>
  </pb_type>

  <interconnect>
   <!-- SB_IO inputs -->
   <direct>
    <port from="current" name="D_IN" bit="0"/>
    <port from="parent" name="D_IN" bit="0"/>
   </direct>
   <direct>
    <port from="current" name="D_IN" bit="1"/>
    <port from="parent" name="D_IN" bit="1"/>
   </direct>
   <direct>
    <port from="current" name="PIN"/>
    <port from="parent" name="PACKAGE_PIN"/>
   </direct>
  </interconnect>

 </mode>

 <metadata>
  <meta name="hlc_cell">io</meta>
  <meta name="hlc_tile">io_tile</meta>
 </metadata>

 <pinlocations pattern="custom">
  <loc side="right" xoffset="0" yoffset="0">
    <port name="D_IN"/>
    <port name="D_OUT"/>
    <port name="OUT_ENB"/>
    <port name="CEN"/>
    <port name="INCLK"/>
    <port name="OUTCLK"/>
    <port name="LATCH"/>
    <port name="PACKAGE_PIN"/>
  </loc>
 </pinlocations>
 <fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0" />
</pb_type>