# Pastebin bVDYvlwo
diff --git a/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v b/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v
index 2efc38c..486873c 100644
--- a/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v
+++ b/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v
@@ -214947,7 +214947,7 @@ module TLDebugModule( // @[freechips.rocketchip.system.LitexConfig.fir 230027:2]
     .auto_dmInner_tl_in_d_bits_source(dmInner_auto_dmInner_tl_in_d_bits_source),
     .auto_dmInner_tl_in_d_bits_data(dmInner_auto_dmInner_tl_in_d_bits_data),
     .io_debug_clock(dmInner_io_debug_clock),
-    .io_debug_reset(dmInner_io_debug_reset),
+    .io_debug_reset(1'b1),
     .io_dmactive(dmInner_io_dmactive),
     .io_innerCtrl_mem_0_resumereq(dmInner_io_innerCtrl_mem_0_resumereq),
     .io_innerCtrl_mem_0_ackhavereset(dmInner_io_innerCtrl_mem_0_ackhavereset),