# Pastebin Z1GXHgPi
module top(input clk, output [7:0] led, output [13:0] disp);

    wire clk1, clk2, clk3, clk4, locked, int_locked;
    (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
    EHXPLLL #(
        .PLLRST_ENA("DISABLED"),
        .INTFB_WAKE("DISABLED"),
        .STDBY_ENABLE("DISABLED"),
        .DPHASE_SOURCE("DISABLED"),
        .CLKOS_FPHASE(0),
        .CLKOP_FPHASE(0),
        .CLKOS3_CPHASE(2),
        .CLKOS2_CPHASE(3),
        .CLKOS_CPHASE(5),
        .CLKOP_CPHASE(11),
        .OUTDIVIDER_MUXD("DIVD"),
        .OUTDIVIDER_MUXC("DIVC"),
        .OUTDIVIDER_MUXB("DIVB"),
        .OUTDIVIDER_MUXA("DIVA"),
        .CLKOS3_ENABLE("ENABLED"),
        .CLKOS2_ENABLE("ENABLED"),
        .CLKOS_ENABLE("ENABLED"),
        .CLKOP_ENABLE("ENABLED"),
        .CLKOS3_DIV(3),
        .CLKOS2_DIV(4),
        .CLKOS_DIV(6),
        .CLKOP_DIV(12),
        .CLKFB_DIV(1),
        .CLKI_DIV(2),
        .FEEDBK_PATH("CLKOP")
    ) pll_i (
        .CLKI(clk),
        .CLKFB(clk1),
        .CLKOP(clk1),
        .CLKOS(clk2),
        .CLKOS2(clk3), 
        .CLKOS3(clk4),
        .RST(1'b0),
        .STDBY(1'b0),
        .PHASESEL0(1'b0),
        .PHASESEL1(1'b0),
        .PHASEDIR(1'b0),
        .PHASESTEP(1'b0),
        .PLLWAKESYNC(1'b0),
        .ENCLKOP(1'b0),
        .ENCLKOS(1'b0),
        .ENCLKOS2(1'b0),
        .ENCLKOS3(1'b0),
        .LOCK(locked),
        .INTLOCK(int_locked)
    );

    reg [26:0] ctr0, ctr1, ctr2, ctr3, ctr4;
    
    always @(posedge clk) ctr0 <= ctr0 + 1;
    always @(posedge clk1) ctr1 <= ctr1 + 1;
    always @(posedge clk2) ctr2 <= ctr2 + 1;
    always @(posedge clk3) ctr3 <= ctr3 + 1;
    always @(posedge clk4) ctr4 <= ctr4 + 1;
    
    assign led = {1'b1, !int_locked, !locked, !ctr4[26], !ctr3[26], !ctr2[26], !ctr1[26], !ctr0[26]};

    assign disp = 14'h3FFF;

endmodule