# Pastebin Umb3BfTC __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| (c) Copyright 2012-2019 Enjoy-Digital BIOS built on Oct 29 2019 14:47:41 BIOS CRC passed (e2c90b23) Migen git sha1: -------- LiteX git sha1: 9fcf2973 --=============== SoC ==================-- CPU: RocketRV64[imac] @ 58MHz ROM: 64KB SRAM: 4KB MAIN-RAM: 524288KB --========== Initialization ============-- Ethernet init... Initializing SDRAM... SDRAM now under software control Read leveling: m0, b0: |11100000| delays: 01+-01 best: m0, b0 delays: 01+-01 m1, b0: |11100000| delays: 01+-01 best: m1, b0 delays: 01+-01 m2, b0: |11100000| delays: 01+-01 best: m2, b0 delays: 01+-01 m3, b0: |01100000| delays: 02+-01 best: m3, b0 delays: 02+-01 SDRAM now under hardware control Memtest OK