# Pastebin UeBvpuIW
mkdir -p build/tinyfpga_bx_usbtest_picorv32.minimal/
time python -u ./make.py --platform=tinyfpga_bx --target=usbtest --cpu-type=picorv32 --iprange=192.168.100   --cpu-variant=minimal --cpu-variant=minimal  \
        2>&1 | tee -a /usr/local/google/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usbtest_picorv32.minimal//output.20181125-131715.log; (exit ${PIPESTATUS[0]})
available clock domains:
crg_sys
crg_usb_48
por
usb_sys
usb_usb_48
scope
Traceback (most recent call last):
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/gen/fhdl/verilog.py", line 365, in convert
    f.clock_domains[cd_name]
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/migen/migen/fhdl/structure.py", line 739, in __getitem__
    raise KeyError(key)
KeyError: 'sys'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "./make.py", line 164, in <module>
    main()
  File "./make.py", line 148, in main
    vns = builder.build(**dict(args.build_option))
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 171, in build
    toolchain_path=toolchain_path, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 389, in build
    return self.platform.build(self, *args, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 29, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/build/lattice/icestorm.py", line 139, in build
    v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 26, in get_verilog
    **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
    create_clock_domains=False, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/gen/fhdl/verilog.py", line 375, in convert
    raise KeyError("Unresolved clock domain: '"+cd_name+"'")
KeyError: "Unresolved clock domain: 'sys'"

real    0m0.327s
user    0m0.270s
sys     0m0.040s