# Pastebin UbzqG8pj
module top(input rclk, wclk, wen, input [9:0] waddr, input [1:0] wdata, input [7:0] raddr, output reg [15:0] rdata);

reg [15:0] memory[0:255];

always @(posedge wclk)
	if (wen)
		memory[waddr[9:3]][2 * waddr[2:0] +: 2] <= wdata;

always @(posedge rclk)
	rdata <= memory[raddr];

endmodule