# Pastebin Irxi3P01

 <fc in_type="abs" in_val="2" out_type="abs" out_val="1"/>   <<--- One output pin is connected to tracks
 <fc in_type="abs" in_val="2" out_type="abs" out_val="2"/>   <<--- Two output pins are connected to tracks
 <fc in_type="abs" in_val="1" out_type="abs" out_val="2"/>   <<--- Half input pins are missing tracks....

I found the following things;

 * The fan-in of the switch depends on the architecture (unidirectional/bidirectional), as well as Fc_in/out and Fs.

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https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/4a20e7b00ade19c5ad0a5b1a85814214a0238e4c/vpr/src/base/vpr_api.cpp#L835-L857

    /* Estimates of switch fan-in are done as follows:
       1) opin to wire switch:
            2 CLBs connect to a channel, each with #opins/4 pins. Each pin has Fc_out*W
            switches, and then we assume the switches are distributed evenly over the W wires.
            In the unidirectional case, all these switches are then crammed down to W/wire_segment_length wires.

                    Unidirectional: 2 * #opins_per_side * Fc_out * wire_segment_length
                    Bidirectional:  2 * #opins_per_side * Fc_out

       2) wire to wire switch
            A wire segment in a switchblock connects to Fs other wires. Assuming these connections are evenly
            distributed, each target wire receives Fs connections as well. In the unidirectional case,
            source wires can only connect to W/wire_segment_length wires.

                    Unidirectional: Fs * wire_segment_length
                    Bidirectional:  Fs

       3) wire to ipin switch
            An input pin of a CLB simply receives Fc_in connections.

                    Unidirectional: Fc_in
                    Bidirectional:  Fc_in
     */


    /* Fan-in to opin/ipin/wire switches depends on whether the architecture is unidirectional/bidirectional */
    (*opin_switch_fanin) = 2 * type->num_drivers / 4 * Fc_out;
    (*wire_switch_fanin) = Fs;
    (*ipin_switch_fanin) = Fc_in;
    if (directionality == UNI_DIRECTIONAL) {
        /* adjustments to opin-to-wire and wire-to-wire switch fan-ins */
        (*opin_switch_fanin) *= wire_segment_length;
        (*wire_switch_fanin) *= wire_segment_length;
    } else if (directionality == BI_DIRECTIONAL) {
        /* no adjustments need to be made here */
    } else {
        vpr_throw(VPR_ERROR_PACK, __FILE__, __LINE__, "Unrecognized directionality: %d\n", (int) directionality);
    }

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https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/7a65c87d8e444985438273e191bd6e72e4c2ec1b/libs/libarchfpga/src/read_xml_arch_file.cpp#L1632-L1715

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https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/05da4af1825deda3874c41ce2f66ed004627eade/vpr/src/route/check_rr_graph.cpp#L175

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