# Pastebin CvNIsWTH
#!/usr/bin/env python3


import argparse

from migen import *

from litex.build.generic_platform import *
from litex.build.xilinx.platform import XilinxPlatform
from litex.build.altera.platform import AlteraPlatform
from litex.build.lattice.platform import LatticePlatform

from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCBusHandler, SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *

from litex.soc.cores.uart import *

# IOs ----------------------------------------------------------------------------------------------

_io = [
    # Clk / Rst.
    ("clk", 0, Pins(1)),
    ("rst", 1, Pins(1)),

    # UART.
    ("uart", 0,
        Subsignal("tx", Pins(1)),
        Subsignal("rx", Pins(1)),
    ),

]

# UART Core ----------------------------------------------------------------------------------

class UARTCore(SoCMini):
    def __init__(self, platform, clk_freq=int(100e6)):
        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = CRG(platform.request("clk"), platform.request("rst"))

        # SoCMini ----------------------------------------------------------------------------------
        SoCMini.__init__(self, platform, clk_freq=clk_freq)

        # Wishbone Control -------------------------------------------------------------------------
        # Create Wishbone Control Slave interface, expose it and connect it to the SoC.
        wb_ctrl = wishbone.Interface()
        self.add_wb_master(wb_ctrl)
        platform.add_extension(wb_ctrl.get_ios("wb_ctrl"))
        self.comb += wb_ctrl.connect_to_pads(self.platform.request("wb_ctrl"), mode="slave")

        # UART -------------------------------------------------------------------------------------
        uart_pads = platform.request("uart")
        self.submodules.uart_phy = UARTPHY(uart_pads, clk_freq=self.sys_clk_freq, baudrate=115200)
        self.submodules.uart     = UART(self.uart_phy)

# Build --------------------------------------------------------------------------------------------

def main():
    parser = argparse.ArgumentParser(description="UART standalone core generator.")
    parser.add_argument("--clk-freq", default="100e6",  help="Input Clk Frequency.")
    parser.add_argument("--vendor",   default="xilinx", help="FPGA Vendor.")
    args = parser.parse_args()

    # Convert/Check Arguments ----------------------------------------------------------------------------
    clk_freq     = int(float(args.clk_freq))
    platform_cls = {
        "xilinx"  : XilinxPlatform,
        "altera"  : AlteraPlatform,
        "intel"   : AlteraPlatform,
        "lattice" : LatticePlatform
    }[args.vendor]

    # Generate core --------------------------------------------------------------------------------
    platform = platform_cls(device="", io=_io)
    core     = UARTCore(platform, clk_freq=clk_freq)
    builder  = Builder(core, output_dir="build")
    builder.build(build_name="uart_core", run=False)

if __name__ == "__main__":
    main()