# Pastebin BVziwS2c
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   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Oct 13 2020 11:44:24
 BIOS CRC passed (c9789cdf)

 Migen git sha1: --------
 LiteX git sha1: 4d553a6f

--=============== SoC ==================--
CPU:		VexRiscv @ 125MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		32KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		1048576KiB 64-bit @ 1000MT/s (CL-9 CWL-9)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
  Cmd/Clk scan:
  |00000000  |0000  |0000  |0000| best: -1
  Setting Cmd/Clk delay to -1 taps.
  Data scan:
  m0: |1111111111111000000000| delay: -
  m1: |1111111111110000000000| delay: -
  m2: |1111111110000000000000| delay: -
  m3: |1111100000000000000000| delay: -
  m4: |0000000000011111111111| delay: 174
  m5: |0000000000000000001111| delay: 280
  m6: |1000000000000000000011| delay: 312
  m7: |1000000000000000000011| delay: 308
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:0 m5:0 m6:0 m7:0 
Read leveling:
  m0, b0: |00000000000000000000000000000000| delays: -
  m0, b1: |00000000000000000000000000000000| delays: -
  m0, b2: |00000000000000000000000000000000| delays: -
  m0, b3: |11111111110000000000000000000000| delays: 71+-71
  m0, b4: |00000000000111111111111111110000| delays: 301+-129
  m0, b5: |00000000000000000000000000000011| delays: 486+-26
  m0, b6: |00000000000000000000000000000000| delays: -
  m0, b7: |00000000000000000000000000000000| delays: -
  best: m0, b04 delays: 300+-129
  m1, b0: |00000000000000000000000000000000| delays: -
  m1, b1: |00000000000000000000000000000000| delays: -
  m1, b2: |00000000000000000000000000000000| delays: -
  m1, b3: |11111111111111000000000000000000| delays: 102+-102
  m1, b4: |00000000000000000111111111111111| delays: 377+-122
  m1, b5: |00000000000000000000000000000000| delays: -
  m1, b6: |00000000000000000000000000000000| delays: -
  m1, b7: |00000000000000000000000000000000| delays: -
  best: m1, b04 delays: 381+-121
  m2, b0: |00000000000000000000000000000000| delays: -
  m2, b1: |00000000000000000000000000000000| delays: -
  m2, b2: |00000000000000000000000000000000| delays: -
  m2, b3: |01111111111111110000000000000000| delays: 128+-124
  m2, b4: |00000000000000000000111111111111| delays: 406+-105
  m2, b5: |00000000000000000000000000000000| delays: -
  m2, b6: |00000000000000000000000000000000| delays: -
  m2, b7: |00000000000000000000000000000000| delays: -
  best: m2, b03 delays: 129+-126
  m3, b0: |00000000000000000000000000000000| delays: -
  m3, b1: |00000000000000000000000000000000| delays: -
  m3, b2: |10000000000000000000000000000000| delays: 08+-08
  m3, b3: |00001111111111111110000000000000| delays: 164+-121
  m3, b4: |00000000000000000000001111111111| delays: 417+-95
  m3, b5: |00000000000000000000000000000000| delays: -
  m3, b6: |00000000000000000000000000000000| delays: -
  m3, b7: |00000000000000000000000000000000| delays: -
  best: m3, b03 delays: 165+-121
  m4, b0: |00000000000000000000000000000000| delays: -
  m4, b1: |00000000000000000000000000000000| delays: -
  m4, b2: |00000000000000000000000000000000| delays: -
  m4, b3: |01111111111111111000000000000000| delays: 134+-121
  m4, b4: |00000000000000000001111111111111| delays: 408+-103
  m4, b5: |00000000000000000000000000000000| delays: -
  m4, b6: |00000000000000000000000000000000| delays: -
  m4, b7: |00000000000000000000000000000000| delays: -
  best: m4, b03 delays: 134+-127
  m5, b0: |00000000000000000000000000000000| delays: -
  m5, b1: |00000000000000000000000000000000| delays: -
  m5, b2: |00000000000000000000000000000000| delays: -
  m5, b3: |11111111111000000000000000000000| delays: 84+-84
  m5, b4: |00000000000000111111111111111000| delays: 333+-118
  m5, b5: |00000000000000000000000000000000| delays: 503+-09
  m5, b6: |00000000000000000000000000000000| delays: -
  m5, b7: |00000000000000000000000000000000| delays: -
  best: m5, b04 delays: 334+-118
  m6, b0: |00000000000000000000000000000000| delays: -
  m6, b1: |00000000000000000000000000000000| delays: -
  m6, b2: |00000000000000000000000000000000| delays: -
  m6, b3: |11111110000000000000000000000000| delays: 53+-53
  m6, b4: |00000000001111111111111110000000| delays: 263+-127
  m6, b5: |00000000000000000000000000001111| delays: 473+-39
  m6, b6: |00000000000000000000000000000000| delays: -
  m6, b7: |00000000000000000000000000000000| delays: -
  best: m6, b04 delays: 265+-127
  m7, b0: |00000000000000000000000000000000| delays: -
  m7, b1: |00000000000000000000000000000000| delays: -
  m7, b2: |00000000000000000000000000000000| delays: -
  m7, b3: |11110000000000000000000000000000| delays: 31+-31
  m7, b4: |00000001111111111111111000000000| delays: 228+-125
  m7, b5: |00000000000000000000000001111111| delays: 448+-64
  m7, b6: |00000000000000000000000000000000| delays: -
  m7, b7: |00000000000000000000000000000000| delays: -
  best: m7, b04 delays: 230+-125
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB     
   Read: 0x40000000-0x40200000 2MiB     
Memtest OK
Memspeed at 0x40000000 (2MiB)...
  Write speed: 38MiB/s
   Read speed: 33MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
No boot medium found

--============= Console ================--

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