{"body":"From 09dcf9bbe80444bac727f905788aef4e9defc3cd Mon Sep 17 00:00:00 2001\nFrom: Florent Kermarrec <florent@enjoy-digital.fr>\nDate: Fri, 26 Nov 2021 09:06:15 +0100\nSubject: [PATCH] Integrate/Fix ejcspii's wb_test_slave.v.\n\ncd litex/soc/tools\n./litex_sim.py\n        __   _ __      _  __\n       / /  (_) /____ | |/_/\n      / /__/ / __/ -_)>  <\n     /____/_/\\__/\\__/_/|_|\n   Build your hardware, easily!\n\n (c) Copyright 2012-2021 Enjoy-Digital\n (c) Copyright 2007-2015 M-Labs\n\n BIOS built on Nov 26 2021 09:02:59\n BIOS CRC passed (825dea61)\n\n Migen git sha1: 9a0be7a\n LiteX git sha1: 85d6cb4b\n\n--=============== SoC ==================--\nCPU:\t\tVexRiscv @ 1MHz\nBUS:\t\tWISHBONE 32-bit @ 4GiB\nCSR:\t\t32-bit data\nROM:\t\t128KiB\nSRAM:\t\t8KiB\n\n\n--============== Boot ==================--\nBooting from serial...\nPress Q or ESC to abort boot completely.\nsL5DdSMmkekro\nTimeout\nNo boot medium found\n\n--============= Console ================--\n\nlitex> mem_list\nAvailable memory regions:\nROM       0x00000000 0x20000\nSRAM      0x10000000 0x2000\nWB_TEST_SLAVE  0x80000000 0x10\nCSR       0xf0000000 0x10000\n\nlitex> mem_read 0x80000000 0x10\nMemory dump:\n0x80000000  20 00 00 00 de c0 ad 0b de c0 ad 0b de c0 ad 0b   ...............\n---\n litex/tools/litex_sim.py        | 21 ++++++++++++++\n litex/tools/rtl/wb_test_slave.v | 49 +++++++++++++++++++++++++++++++++\n 2 files changed, 70 insertions(+)\n create mode 100644 litex/tools/rtl/wb_test_slave.v\n\ndiff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py\nindex 51905809..ac4663fa 100755\n--- a/litex/tools/litex_sim.py\n+++ b/litex/tools/litex_sim.py\n@@ -303,6 +303,27 @@ class SimSoC(SoCCore):\n         else:\n             self.comb += platform.trace.eq(1)\n \n+\n+        class TestModule(Module):\n+            def __init__(self, platform):\n+                self.bus = bus = wishbone.Interface(data_width=32, adr_width=29)\n+                self.specials += Instance(\"wb_test_slave\",\n+                    i_i_reset   = ResetSignal(\"sys\"),\n+                    i_i_clk     = ClockSignal(\"sys\"),\n+                    i_i_wb_cyc  = bus.cyc,\n+                    i_i_wb_stb  = bus.stb,\n+                    i_i_wb_we   = bus.we,\n+                    i_i_wb_addr = bus.adr,\n+                    i_i_wb_data = bus.dat_w,\n+                    o_o_wb_data = bus.dat_r,\n+                    o_o_wb_ack  = bus.ack,\n+                    #o_o_wb_err = bus.err,\n+                )\n+                platform.add_source(\"rtl/wb_test_slave.v\")\n+\n+        self.submodules.wb_test_slave = TestModule(platform)\n+        self.bus.add_slave(name=\"wb_test_slave\", slave=self.wb_test_slave.bus, region=SoCRegion(size=16, cached=False))\n+\n # Build --------------------------------------------------------------------------------------------\n \n def generate_gtkw_savefile(builder, vns, trace_fst):\ndiff --git a/litex/tools/rtl/wb_test_slave.v b/litex/tools/rtl/wb_test_slave.v\nnew file mode 100644\nindex 00000000..3a75a0aa\n--- /dev/null\n+++ b/litex/tools/rtl/wb_test_slave.v\n@@ -0,0 +1,49 @@\n+module wb_test_slave\n+(\n+                input   wire                i_clk, i_reset,\n+                // Wishbone inputs\n+                input   wire                i_wb_cyc,\n+                input   wire                i_wb_stb, i_wb_we,\n+                input   wire    [31:0]  i_wb_addr,\n+                input   wire    [31:0]  i_wb_data,\n+                input   wire    [3:0]   i_wb_sel,\n+                output  wire                o_wb_stall,\n+                output  reg                     o_wb_ack,\n+                output  reg         [31:0]      o_wb_data\n+        //output  wire            o_wb_err\n+        //\n+);\n+\n+    reg [31:0] regs;\n+  always @(posedge i_clk)\n+    begin\n+        if(i_reset == 1'b1)\n+            regs <= 32'b0;\n+        else if (i_wb_stb && i_wb_we && !o_wb_stall)\n+        begin\n+            regs <= i_wb_data;\n+        end\n+    end\n+\n+    always @(posedge i_clk)\n+    begin\n+        case(i_wb_addr)\n+            32'h0: o_wb_data <= regs;\n+            default: o_wb_data <= 32'h0badc0de;\n+        endcase\n+    end\n+\n+    assign o_wb_stall = 1'b0;\n+\n+   always @(posedge i_clk)\n+    if (i_reset)\n+        o_wb_ack <= 1'b0;\n+    else\n+        o_wb_ack <= (i_wb_stb && i_wb_cyc && !o_wb_stall);\n+\n+\twire _unused_ok = &{1'b0,\n+                    i_wb_cyc,\n+                    i_wb_sel,\n+                    1'b0};\n+\n+endmodule\n\\ No newline at end of file\n-- \n2.17.1\n\n","name":"","extension":"txt","url":"https://www.irccloud.com/pastebin/zmkn1VFM","modified":1637914065,"id":"zmkn1VFM","size":4398,"lines":146,"own_paste":false,"theme":"","date":1637914065}