{"body":"\\section{Instruction set}\n\\subsection{Core instructions}\n\n\\begin{tabular}{ |l|l| }\n  \\hline\n  \\multicolumn{2}{|c|}{BMIU core microcode instruction set} \\\\\n  \\hline\n\\textbf{IM} & Push immediate number onto stack \\\\\n\\textbf{FM} & Fetch memory onto stack \\\\\n\\textbf{LM} & Load memory from stack \\\\\n\\textbf{CP} & Complete procedure \\\\\n  \\hline\n\\end{tabular}\n\nThe BMIU architecture consists of an inner and outer control unit. The inner control unit operates on microcode located in the first 1K of memory between address $0000 and $04FF. The outer control unit reads from the memory address of the 16 bit program counter at $600, obtaining a pointer to microcode stored in the in memory programmable decoder at address $0500 - $05FF. The offset of the decoder memory is the value retrieved from the address pointed to by the Instruction Pointer register.","name":"","extension":"txt","url":"https://www.irccloud.com/pastebin/x1R1kO3d","modified":1509899388,"id":"x1R1kO3d","size":850,"lines":15,"own_paste":false,"theme":"","date":1509899388}