{"body":"Debug: 176 5 target.c:1308 handle_target_init_command(): Initializing targets...\nDebug: 177 5 or1k.c:517 or1k_build_reg_cache(): -\nDebug: 178 6 command.c:366 register_command_handler(): registering 'ocd_target_request'...\nDebug: 179 6 command.c:366 register_command_handler(): registering 'ocd_trace'...\nDebug: 180 6 command.c:366 register_command_handler(): registering 'ocd_trace'...\nDebug: 181 6 command.c:366 register_command_handler(): registering 'ocd_fast_load_image'...\nDebug: 182 6 command.c:366 register_command_handler(): registering 'ocd_fast_load'...\nDebug: 183 6 command.c:366 register_command_handler(): registering 'ocd_profile'...\nDebug: 184 6 command.c:366 register_command_handler(): registering 'ocd_virt2phys'...\nDebug: 185 6 command.c:366 register_command_handler(): registering 'ocd_reg'...\nDebug: 186 6 command.c:366 register_command_handler(): registering 'ocd_poll'...\nDebug: 187 6 command.c:366 register_command_handler(): registering 'ocd_wait_halt'...\nDebug: 188 6 command.c:366 register_command_handler(): registering 'ocd_halt'...\nDebug: 189 6 command.c:366 register_command_handler(): registering 'ocd_resume'...\nDebug: 190 6 command.c:366 register_command_handler(): registering 'ocd_reset'...\nDebug: 191 6 command.c:366 register_command_handler(): registering 'ocd_soft_reset_halt'...\nDebug: 192 6 command.c:366 register_command_handler(): registering 'ocd_step'...\nDebug: 193 6 command.c:366 register_command_handler(): registering 'ocd_mdw'...\nDebug: 194 6 command.c:366 register_command_handler(): registering 'ocd_mdh'...\nDebug: 195 6 command.c:366 register_command_handler(): registering 'ocd_mdb'...\nDebug: 196 6 command.c:366 register_command_handler(): registering 'ocd_mww'...\nDebug: 197 6 command.c:366 register_command_handler(): registering 'ocd_mwh'...\nDebug: 198 6 command.c:366 register_command_handler(): registering 'ocd_mwb'...\nDebug: 199 6 command.c:366 register_command_handler(): registering 'ocd_bp'...\nDebug: 200 6 command.c:366 register_command_handler(): registering 'ocd_rbp'...\nDebug: 201 6 command.c:366 register_command_handler(): registering 'ocd_wp'...\nDebug: 202 6 command.c:366 register_command_handler(): registering 'ocd_rwp'...\nDebug: 203 6 command.c:366 register_command_handler(): registering 'ocd_load_image'...\nDebug: 204 6 command.c:366 register_command_handler(): registering 'ocd_dump_image'...\nDebug: 205 6 command.c:366 register_command_handler(): registering 'ocd_verify_image'...\nDebug: 206 6 command.c:366 register_command_handler(): registering 'ocd_test_image'...\nDebug: 207 6 command.c:366 register_command_handler(): registering 'ocd_reset_nag'...\nDebug: 208 6 command.c:366 register_command_handler(): registering 'ocd_ps'...\nDebug: 209 6 command.c:366 register_command_handler(): registering 'ocd_test_mem_access'...\nDebug: 210 6 ftdi.c:630 ftdi_initialize(): ftdi interface using shortest path jtag state transitions\nDebug: 211 10 mpsse.c:363 mpsse_purge(): -\nDebug: 212 11 mpsse.c:644 mpsse_loopback_config(): off\nDebug: 213 11 mpsse.c:689 mpsse_set_frequency(): target 3000000 Hz\nDebug: 214 11 mpsse.c:681 mpsse_rtck_config(): off\nDebug: 215 11 mpsse.c:670 mpsse_divide_by_5_config(): off\nDebug: 216 11 mpsse.c:650 mpsse_set_divisor(): 9\nDebug: 217 11 mpsse.c:713 mpsse_set_frequency(): actually 3000000 Hz\nDebug: 218 11 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value\nDebug: 219 11 core.c:1603 adapter_khz_to_speed(): have interface set up\nDebug: 220 11 mpsse.c:689 mpsse_set_frequency(): target 3000000 Hz\nDebug: 221 11 mpsse.c:681 mpsse_rtck_config(): off\nDebug: 222 11 mpsse.c:670 mpsse_divide_by_5_config(): off\nDebug: 223 11 mpsse.c:650 mpsse_set_divisor(): 9\nDebug: 224 11 mpsse.c:713 mpsse_set_frequency(): actually 3000000 Hz\nDebug: 225 11 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value\nDebug: 226 11 core.c:1603 adapter_khz_to_speed(): have interface set up\nInfo : 227 11 core.c:1388 adapter_init(): clock speed 3000 kHz\nDebug: 228 11 openocd.c:137 handle_init_command(): Debug Adapter init complete\nDebug: 229 11 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport init\nDebug: 230 11 command.c:145 script_debug(): command - ocd_transport ocd_transport init\nDebug: 232 11 transport.c:240 handle_transport_init(): handle_transport_init\nDebug: 233 11 core.c:731 jtag_add_reset(): SRST line released\nDebug: 234 11 core.c:755 jtag_add_reset(): TRST line released\nDebug: 235 11 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset\nDebug: 236 11 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init\nDebug: 237 11 command.c:145 script_debug(): command - ocd_jtag ocd_jtag arp_init\nDebug: 238 11 core.c:1401 jtag_init_inner(): Init JTAG chain\nDebug: 239 11 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset\nDebug: 240 12 core.c:1062 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS\nDebug: 241 12 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset\nInfo : 242 12 core.c:961 jtag_examine_chain_display(): JTAG tap: or1200.cpu tap/device found: 0x44008093 (mfg: 0x049 (Xilinx), part: 0x4008, ver: 0x4)\nDebug: 243 12 core.c:1192 jtag_validate_ircapture(): IR capture validation scan\nDebug: 244 12 core.c:1250 jtag_validate_ircapture(): or1200.cpu: IR capture 0x35\nDebug: 245 13 openocd.c:150 handle_init_command(): Examining targets...\nDebug: 246 13 target.c:1501 target_call_event_callbacks(): target event 21 (examine-start)\nDebug: 247 13 or1k_tap_xilinx_bscan.c:29 or1k_tap_xilinx_bscan_init(): Initialising Xilinx Internal JTAG TAP\nDebug: 248 13 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset\nInfo : 249 13 or1k_du_adv.c:198 or1k_adv_jtag_init(): adv debug unit is configured with option ADBG_USE_HISPEED\nInfo : 250 13 or1k_du_adv.c:202 or1k_adv_jtag_init(): adv debug unit is configured with option ENABLE_JSP_MULTI\nInfo : 251 13 or1k_du_adv.c:203 or1k_adv_jtag_init(): adv debug unit is configured with option ENABLE_JSP_SERVER\nDebug: 252 13 or1k_du_adv.c:211 or1k_adv_jtag_init(): Init done\nDebug: 253 13 or1k_du_adv.c:230 adbg_select_module(): Select module: CPU0\nDebug: 254 13 target.c:1501 target_call_event_callbacks(): target event 22 (examine-end)\nDebug: 255 13 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash init\nDebug: 256 13 command.c:145 script_debug(): command - ocd_flash ocd_flash init\nDebug: 258 14 tcl.c:1067 handle_flash_init_command(): Initializing flash devices...\nDebug: 259 14 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mflash init\nDebug: 260 14 command.c:145 script_debug(): command - ocd_mflash ocd_mflash init\nDebug: 262 14 mflash.c:1379 handle_mflash_init_command(): Initializing mflash devices...\nDebug: 263 14 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_nand init\nDebug: 264 14 command.c:145 script_debug(): command - ocd_nand ocd_nand init\nDebug: 266 14 tcl.c:497 handle_nand_init_command(): Initializing NAND devices...\nDebug: 267 14 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_pld init\nDebug: 268 14 command.c:145 script_debug(): command - ocd_pld ocd_pld init\nDebug: 270 14 pld.c:207 handle_pld_init_command(): Initializing PLDs...\nDebug: 271 14 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_echo Halting processor\nDebug: 272 14 command.c:145 script_debug(): command - echo ocd_echo Halting processor\nUser : 274 14 command.c:764 jim_echo(): Halting processor\nDebug: 275 15 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_halt\nDebug: 276 15 command.c:145 script_debug(): command - halt ocd_halt\nDebug: 278 15 target.c:2806 handle_halt_command(): -\nDebug: 279 15 or1k.c:579 or1k_halt(): target->state: running\nDebug: 280 15 or1k_du_adv.c:313 adbg_ctrl_write(): Write control register 0: 0x00000001\nDebug: 281 16 or1k.c:554 or1k_debug_entry(): -\nDebug: 282 16 or1k.c:344 or1k_save_context(): -\nDebug: 283 16 or1k.c:319 or1k_jtag_read_regs(): -\nDebug: 284 16 or1k_du_adv.c:450 adbg_wb_burst_read(): Doing burst read, word size 4, word count 32, start address 0x00000400\nDebug: 285 16 or1k_du_adv.c:547 adbg_wb_burst_read(): CRC OK!\nDebug: 286 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 287 16 or1k.c:423 or1k_read_core_reg(): Read core reg 0 value 0x00000000\nDebug: 288 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 289 16 or1k.c:423 or1k_read_core_reg(): Read core reg 1 value 0x10000f88\nDebug: 290 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 291 16 or1k.c:423 or1k_read_core_reg(): Read core reg 2 value 0xe0000000\nDebug: 292 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 293 16 or1k.c:423 or1k_read_core_reg(): Read core reg 3 value 0x00067f00\nDebug: 294 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 295 16 or1k.c:423 or1k_read_core_reg(): Read core reg 4 value 0x0000003d\nDebug: 296 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 297 16 or1k.c:423 or1k_read_core_reg(): Read core reg 5 value 0xe0002020\nDebug: 298 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 299 16 or1k.c:423 or1k_read_core_reg(): Read core reg 6 value 0x0009ef21\nDebug: 300 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 301 16 or1k.c:423 or1k_read_core_reg(): Read core reg 7 value 0x10000014\nDebug: 302 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 303 16 or1k.c:423 or1k_read_core_reg(): Read core reg 8 value 0x00000000\nDebug: 304 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 305 16 or1k.c:423 or1k_read_core_reg(): Read core reg 9 value 0x000020b8\nDebug: 306 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 307 16 or1k.c:423 or1k_read_core_reg(): Read core reg 10 value 0x00000100\nDebug: 308 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 309 16 or1k.c:423 or1k_read_core_reg(): Read core reg 11 value 0x00000000\nDebug: 310 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 311 16 or1k.c:423 or1k_read_core_reg(): Read core reg 12 value 0x00000000\nDebug: 312 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 313 16 or1k.c:423 or1k_read_core_reg(): Read core reg 13 value 0x00000002\nDebug: 314 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 315 16 or1k.c:423 or1k_read_core_reg(): Read core reg 14 value 0xe0002030\nDebug: 316 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 317 16 or1k.c:423 or1k_read_core_reg(): Read core reg 15 value 0x00000000\nDebug: 318 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 319 16 or1k.c:423 or1k_read_core_reg(): Read core reg 16 value 0x00000000\nDebug: 320 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 321 16 or1k.c:423 or1k_read_core_reg(): Read core reg 17 value 0x00000002\nDebug: 322 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 323 16 or1k.c:423 or1k_read_core_reg(): Read core reg 18 value 0xe000202c\nDebug: 324 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 325 16 or1k.c:423 or1k_read_core_reg(): Read core reg 19 value 0x000057a4\nDebug: 326 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 327 16 or1k.c:423 or1k_read_core_reg(): Read core reg 20 value 0xe0002028\nDebug: 328 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 329 16 or1k.c:423 or1k_read_core_reg(): Read core reg 21 value 0x00000020\nDebug: 330 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 331 16 or1k.c:423 or1k_read_core_reg(): Read core reg 22 value 0x00000000\nDebug: 332 16 or1k.c:415 or1k_read_core_reg(): -\nDebug: 333 16 or1k.c:423 or1k_read_core_reg(): Read core reg 23 value 0x00000000\nDebug: 334 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 335 17 or1k.c:423 or1k_read_core_reg(): Read core reg 24 value 0x00000000\nDebug: 336 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 337 17 or1k.c:423 or1k_read_core_reg(): Read core reg 25 value 0x00000000\nDebug: 338 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 339 17 or1k.c:423 or1k_read_core_reg(): Read core reg 26 value 0x00000000\nDebug: 340 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 341 17 or1k.c:423 or1k_read_core_reg(): Read core reg 27 value 0x00000000\nDebug: 342 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 343 17 or1k.c:423 or1k_read_core_reg(): Read core reg 28 value 0x00000000\nDebug: 344 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 345 17 or1k.c:423 or1k_read_core_reg(): Read core reg 29 value 0x00000000\nDebug: 346 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 347 17 or1k.c:423 or1k_read_core_reg(): Read core reg 30 value 0x00000000\nDebug: 348 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 349 17 or1k.c:423 or1k_read_core_reg(): Read core reg 31 value 0x00000000\nDebug: 350 17 or1k_du_adv.c:450 adbg_wb_burst_read(): Doing burst read, word size 4, word count 1, start address 0x00000012\nDebug: 351 17 or1k_du_adv.c:547 adbg_wb_burst_read(): CRC OK!\nDebug: 352 17 or1k.c:415 or1k_read_core_reg(): -\nDebug: 353 17 or1k.c:423 or1k_read_core_reg(): Read core reg 32 value 0x00002090\nDebug: 354 17 or1k_du_adv.c:450 adbg_wb_burst_read(): Doing burst read, word size 4, word count 1, start address 0x00000010\nDebug: 355 18 or1k_du_adv.c:547 adbg_wb_burst_read(): CRC OK!\nDebug: 356 18 or1k.c:415 or1k_read_core_reg(): -\nDebug: 357 18 or1k.c:423 or1k_read_core_reg(): Read core reg 33 value 0x00002090\nDebug: 358 18 or1k_du_adv.c:450 adbg_wb_burst_read(): Doing burst read, word size 4, word count 1, start address 0x00000011\nDebug: 359 18 or1k_du_adv.c:547 adbg_wb_burst_read(): CRC OK!\nDebug: 360 18 or1k.c:415 or1k_read_core_reg(): -\nDebug: 361 18 or1k.c:423 or1k_read_core_reg(): Read core reg 34 value 0x0000821d\nDebug: 362 18 target.c:1501 target_call_event_callbacks(): target event 0 (gdb-halt)\nDebug: 363 18 target.c:1501 target_call_event_callbacks(): target event 1 (halted)\nUser : 364 18 target.c:1936 target_arch_state(): or1200.cpu: target state: halted\nDebug: 365 18 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target names\nDebug: 366 18 command.c:145 script_debug(): command - ocd_target ocd_target names\nDebug: 367 18 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_or1200.cpu cget -endian\nDebug: 368 18 command.c:145 script_debug(): command - ocd_or1200.cpu ocd_or1200.cpu cget -endian\nDebug: 369 18 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_or1200.cpu cget -type\nDebug: 370 18 command.c:145 script_debug(): command - ocd_or1200.cpu ocd_or1200.cpu cget -type\nChip is or1200.cpu, Endian: big, type: or1k\nTarget ready...\nDebug: 371 18 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_init\nDebug: 372 18 command.c:145 script_debug(): command - init ocd_init\nDebug: 374 19 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_exit\nDebug: 375 19 command.c:145 script_debug(): command - exit ocd_exit\n","name":"","extension":"txt","url":"https://www.irccloud.com/pastebin/lpHVPZVl","modified":1460823136,"id":"lpHVPZVl","size":14541,"lines":194,"own_paste":false,"theme":"","date":1460823136}