{"body":"diff --git a/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v b/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v\nindex 2efc38c..486873c 100644\n--- a/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v\n+++ b/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v\n@@ -214947,7 +214947,7 @@ module TLDebugModule( // @[freechips.rocketchip.system.LitexConfig.fir 230027:2]\n     .auto_dmInner_tl_in_d_bits_source(dmInner_auto_dmInner_tl_in_d_bits_source),\n     .auto_dmInner_tl_in_d_bits_data(dmInner_auto_dmInner_tl_in_d_bits_data),\n     .io_debug_clock(dmInner_io_debug_clock),\n-    .io_debug_reset(dmInner_io_debug_reset),\n+    .io_debug_reset(1'b1),\n     .io_dmactive(dmInner_io_dmactive),\n     .io_innerCtrl_mem_0_resumereq(dmInner_io_innerCtrl_mem_0_resumereq),\n     .io_innerCtrl_mem_0_ackhavereset(dmInner_io_innerCtrl_mem_0_ackhavereset),","name":"","extension":"diff","url":"https://www.irccloud.com/pastebin/bVDYvlwo","modified":1606561332,"id":"bVDYvlwo","size":981,"lines":13,"own_paste":false,"theme":"","date":1606561332}