{"body":"        __   _ __      _  __\n       / /  (_) /____ | |/_/\n      / /__/ / __/ -_)>  <\n     /____/_/\\__/\\__/_/|_|\n   Build your hardware, easily!\n\n (c) Copyright 2012-2020 Enjoy-Digital\n (c) Copyright 2007-2015 M-Labs\n\n BIOS built on Apr 28 2020 15:19:02\n BIOS CRC passed (fe86814d)\n\n Migen git sha1: --------\n LiteX git sha1: 86bedd44\n\n--=============== SoC ==================--\nCPU:       VexRiscv @ 125MHz\nROM:       32KB\nSRAM:      4KB\nL2:        8KB\nMAIN-RAM:  1048576KB\n\n--========== Initialization ============--\nInitializing SDRAM...\nSDRAM now under software control\nWrite leveling:\nCommand/Clk scan:\n|00000000|0000|0000|0000| best: -1\nData scan:\nm0: |1111111111110000000000| delay: -1\nm1: |1111111111100000000000| delay: -1\nm2: |1111111110000000000000| delay: -1\nm3: |1111100000000000000000| delay: -1\nm4: |0000000000011111111111| delay: 175\nm5: |0000000000000000011111| delay: 266\nm6: |0000000000000000000111| delay: 297\nm7: |1000000000000000000011| delay: 309\nRead leveling:\nm0, b0: |00000000000000000000000000000000| delays: -\nm0, b1: |00000000000000000000000000000000| delays: -\nm0, b2: |00000000000000000000000000000000| delays: -\nm0, b3: |00000000000000000000000000000000| delays: -\nm0, b4: |00000000000000000000000000000000| delays: -\nm0, b5: |00000000000000000000000000000000| delays: -\nm0, b6: |00000000000000000000000000000000| delays: -\nm0, b7: |00000000000000000000000000000000| delays: -\nbest: m0, b0 delays: -\nm1, b0: |00000000000000000000000000000000| delays: -\nm1, b1: |00000000000000000000000000000000| delays: -\nm1, b2: |00000000000000000000000000000000| delays: -\nm1, b3: |00000000000000000000000000000000| delays: -\nm1, b4: |00000000000000000000000000000000| delays: -\nm1, b5: |00000000000000000000000000000000| delays: -\nm1, b6: |00000000000000000000000000000000| delays: -\nm1, b7: |00000000000000000000000000000000| delays: -\nbest: m1, b0 delays: -\nm2, b0: |00000000000000000000000000000000| delays: -\nm2, b1: |00000000000000000000000000000000| delays: -\nm2, b2: |00000000000000000000000000000000| delays: -\nm2, b3: |00000000000000000000000000000000| delays: -\nm2, b4: |00000000000000000000000000000000| delays: -\nm2, b5: |00000000000000000000000000000000| delays: -\nm2, b6: |00000000000000000000000000000000| delays: -\nm2, b7: |00000000000000000000000000000000| delays: -\nbest: m2, b0 delays: -\nm3, b0: |00000000000000000000000000000000| delays: -\nm3, b1: |00000000000000000000000000000000| delays: -\nm3, b2: |00000000000000000000000000000000| delays: -\nm3, b3: |00000000000000000000000000000000| delays: -\nm3, b4: |00000000000000000000000000000000| delays: -\nm3, b5: |00000000000000000000000000000000| delays: -\nm3, b6: |00000000000000000000000000000000| delays: -\nm3, b7: |00000000000000000000000000000000| delays: -\nbest: m3, b0 delays: -\nm4, b0: |00000000000000000000000000000000| delays: -\nm4, b1: |00000000000000000000000000000000| delays: -\nm4, b2: |00000000000000000000000000000000| delays: -\nm4, b3: |00000000000000000000000000000000| delays: -\nm4, b4: |00000000000000000000000000000000| delays: -\nm4, b5: |00000000000000000000000000000000| delays: -\nm4, b6: |00000000000000000000000000000000| delays: -\nm4, b7: |00000000000000000000000000000000| delays: -\nbest: m4, b0 delays: -\nm5, b0: |00000000000000000000000000000000| delays: -\nm5, b1: |00000000000000000000000000000000| delays: -\nm5, b2: |00000000000000000000000000000000| delays: -\nm5, b3: |00000000000000000000000000000000| delays: -\nm5, b4: |00000000000000000000000000000000| delays: -\nm5, b5: |00000000000000000000000000000000| delays: -\nm5, b6: |00000000000000000000000000000000| delays: -\nm5, b7: |00000000000000000000000000000000| delays: -\nbest: m5, b0 delays: -\nm6, b0: |00000000000000000000000000000000| delays: -\nm6, b1: |00000000000000000000000000000000| delays: -\nm6, b2: |00000000000000000000000000000000| delays: -\nm6, b3: |00000000000000000000000000000000| delays: -\nm6, b4: |00000000000000000000000000000000| delays: -\nm6, b5: |00000000000000000000000000000000| delays: -\nm6, b6: |00000000000000000000000000000000| delays: -\nm6, b7: |00000000000000000000000000000000| delays: -\nbest: m6, b0 delays: -\nm7, b0: |00000000000000000000000000000000| delays: -\nm7, b1: |00000000000000000000000000000000| delays: -\nm7, b2: |00000000000000000000000000000000| delays: -\nm7, b3: |00000000000000000000000000000000| delays: -\nm7, b4: |00000000000000000000000000000000| delays: -\nm7, b5: |00000000000000000000000000000000| delays: -\nm7, b6: |00000000000000000000000000000000| delays: -\nm7, b7: |00000000000000000000000000000000| delays: -\nbest: m7, b0 delays: -\nSDRAM now under hardware control\nMemtest bus failed: 256/256 errors\nMemtest data failed: 524288/524288 errors\nMemtest addr failed: 8192/8192 errors\nMemory initialization failed","name":"","extension":"txt","url":"https://www.irccloud.com/pastebin/YQVHMpcj","modified":1588084837,"id":"YQVHMpcj","size":4736,"lines":115,"own_paste":false,"theme":"","date":1588084837}