{"body":"/*\n * DMA allocations for non-coherent devices use what the Arm architecture calls\n * \"Normal non-cacheable\" memory, which permits speculation, unaligned accesses\n * and merging of writes.  This is different from \"Device-nGnR[nE]\" memory which\n * is intended for MMIO and thus forbids speculation, preserves access size,\n * requires strict alignment and can also force write responses to come from the\n * endpoint.\n */\n#define pgprot_dmacoherent(prot) \\\n        __pgprot_modify(prot, PTE_ATTRINDX_MASK, \\\n                        PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)","name":"","extension":"txt","url":"https://www.irccloud.com/pastebin/QqrSQmRC","modified":1668502703,"id":"QqrSQmRC","size":576,"lines":11,"own_paste":false,"theme":"","date":1668502703}