{"body":"#!/usr/bin/env python3\n\n\nimport argparse\n\nfrom migen import *\n\nfrom litex.build.generic_platform import *\nfrom litex.build.xilinx.platform import XilinxPlatform\nfrom litex.build.altera.platform import AlteraPlatform\nfrom litex.build.lattice.platform import LatticePlatform\n\nfrom litex.soc.interconnect import wishbone\nfrom litex.soc.integration.soc import SoCBusHandler, SoCRegion\nfrom litex.soc.integration.soc_core import *\nfrom litex.soc.integration.builder import *\n\nfrom litex.soc.cores.uart import *\n\n# IOs ----------------------------------------------------------------------------------------------\n\n_io = [\n    # Clk / Rst.\n    (\"clk\", 0, Pins(1)),\n    (\"rst\", 1, Pins(1)),\n\n    # UART.\n    (\"uart\", 0,\n        Subsignal(\"tx\", Pins(1)),\n        Subsignal(\"rx\", Pins(1)),\n    ),\n\n]\n\n# UART Core ----------------------------------------------------------------------------------\n\nclass UARTCore(SoCMini):\n    def __init__(self, platform, clk_freq=int(100e6)):\n        # CRG --------------------------------------------------------------------------------------\n        self.submodules.crg = CRG(platform.request(\"clk\"), platform.request(\"rst\"))\n\n        # SoCMini ----------------------------------------------------------------------------------\n        SoCMini.__init__(self, platform, clk_freq=clk_freq)\n\n        # Wishbone Control -------------------------------------------------------------------------\n        # Create Wishbone Control Slave interface, expose it and connect it to the SoC.\n        wb_ctrl = wishbone.Interface()\n        self.add_wb_master(wb_ctrl)\n        platform.add_extension(wb_ctrl.get_ios(\"wb_ctrl\"))\n        self.comb += wb_ctrl.connect_to_pads(self.platform.request(\"wb_ctrl\"), mode=\"slave\")\n\n        # UART -------------------------------------------------------------------------------------\n        uart_pads = platform.request(\"uart\")\n        self.submodules.uart_phy = UARTPHY(uart_pads, clk_freq=self.sys_clk_freq, baudrate=115200)\n        self.submodules.uart     = UART(self.uart_phy)\n\n# Build --------------------------------------------------------------------------------------------\n\ndef main():\n    parser = argparse.ArgumentParser(description=\"UART standalone core generator.\")\n    parser.add_argument(\"--clk-freq\", default=\"100e6\",  help=\"Input Clk Frequency.\")\n    parser.add_argument(\"--vendor\",   default=\"xilinx\", help=\"FPGA Vendor.\")\n    args = parser.parse_args()\n\n    # Convert/Check Arguments ----------------------------------------------------------------------------\n    clk_freq     = int(float(args.clk_freq))\n    platform_cls = {\n        \"xilinx\"  : XilinxPlatform,\n        \"altera\"  : AlteraPlatform,\n        \"intel\"   : AlteraPlatform,\n        \"lattice\" : LatticePlatform\n    }[args.vendor]\n\n    # Generate core --------------------------------------------------------------------------------\n    platform = platform_cls(device=\"\", io=_io)\n    core     = UARTCore(platform, clk_freq=clk_freq)\n    builder  = Builder(core, output_dir=\"build\")\n    builder.build(build_name=\"uart_core\", run=False)\n\nif __name__ == \"__main__\":\n    main()\n","name":"","extension":"txt","url":"https://www.irccloud.com/pastebin/CvNIsWTH","modified":1649235036,"id":"CvNIsWTH","size":3105,"lines":81,"own_paste":false,"theme":"","date":1649235036}