{"body":"        __   _ __      _  __\n       / /  (_) /____ | |/_/\n      / /__/ / __/ -_)>  <\n     /____/_/\\__/\\__/_/|_|\n   Build your hardware, easily!\n\n (c) Copyright 2012-2020 Enjoy-Digital\n (c) Copyright 2007-2015 M-Labs\n\n BIOS built on Apr 30 2020 19:21:38\n BIOS CRC passed (f14ae397)\n\n Migen git sha1: 5b5e4fd\n LiteX git sha1: b82b3b7\n\n--=============== SoC ==================--\nCPU:       VexRiscv @ 125MHz\nROM:       32KB\nSRAM:      4KB\nL2:        8KB\nMAIN-RAM:  1048576KB\n\n--========== Initialization ============--\nInitializing SDRAM...\nSDRAM now under software control\nWrite leveling:\nCommand/Clk scan:\n|11111111000000000001111111111111| best: 21\nData scan:\nm0: |00000111111111111000000000| delay: 05\nm1: |00000011111111111100000000| delay: 06\nm2: |00011111111111100000000000| delay: 03\nm3: |00011111111111100000000000| delay: 03\nRead leveling:\nm0, b0: |00000000000000000000000000000000| delays: -\nm0, b1: |00000000000000000000000000000000| delays: -\nm0, b2: |00000000000000000000000000000000| delays: -\nm0, b3: |00000000000000000000000000000000| delays: -\nm0, b4: |00000000000000000000000000000000| delays: -\nm0, b5: |00000000000000000000000000000000| delays: -\nm0, b6: |00000000000000000000000000000000| delays: -\nm0, b7: |00000000000000000000000000000000| delays: -\nbest: m0, b0 delays: -\nm1, b0: |00000000000000000000000000000000| delays: -\nm1, b1: |00000000000000000000000000000000| delays: -\nm1, b2: |00000000000000000000000000000000| delays: -\nm1, b3: |00000000000000000000000000000000| delays: -\nm1, b4: |00000000000000000000000000000000| delays: -\nm1, b5: |00000000000000000000000000000000| delays: -\nm1, b6: |00000000000000000000000000000000| delays: -\nm1, b7: |00000000000000000000000000000000| delays: -\nbest: m1, b0 delays: -\nm2, b0: |00000000000000000000000000000000| delays: -\nm2, b1: |00000000000000000000000000000000| delays: -\nm2, b2: |00000000000000000000000000000000| delays: -\nm2, b3: |00000000000000000000000000000000| delays: -\nm2, b4: |00000000000000000000000000000000| delays: -\nm2, b5: |00000000000000000000000000000000| delays: -\nm2, b6: |00000000000000000000000000000000| delays: -\nm2, b7: |00000000000000000000000000000000| delays: -\nbest: m2, b0 delays: -\nm3, b0: |00000000000000000000000000000000| delays: -\nm3, b1: |00000000000000000000000000000000| delays: -\nm3, b2: |00000000000000000000000000000000| delays: -\nm3, b3: |00000000000000000000000000000000| delays: -\nm3, b4: |00000000000000000000000000000000| delays: -\nm3, b5: |00000000000000000000000000000000| delays: -\nm3, b6: |00000000000000000000000000000000| delays: -\nm3, b7: |00000000000000000000000000000000| delays: -\nbest: m3, b0 delays: -\nSDRAM now under hardware control\nMemtest bus failed: 106/256 errors\nMemtest data failed: 524278/524288 errors\nMemtest addr failed: 8192/8192 errors\nMemory initialization failed\n\n--============= Console ================--\nlitex> help\nLiteX BIOS, available commands:\nmr         - read address space\nmw         - write address space\nmc         - copy address space\n\ncrc        - compute CRC32 of a part of the address space\nident      - display identifier\n\nflush_cpu_dcache - flush CPU data cache\nflush_l2_cache   - flush L2 cache\n\nreboot     - reset processor\nserialboot - boot via SFL\n\nmemtest    - run a memory test\n\nlitex>","name":"Recent_Vex_125MhZ","extension":"txt","url":"https://www.irccloud.com/pastebin/1AIrGhDw/Recent_Vex_125MhZ","modified":1588297991,"id":"1AIrGhDw","size":3258,"lines":95,"own_paste":false,"theme":"","date":1588297991}